George Herold wrote: > On Friday, January 29, 2021 at 2:27:23 PM UTC-5, Phil Hobbs wrote: >> George Herold wrote: >>> On Thursday, January 28, 2021 at 8:34:42 PM UTC-5, Phil Hobbs wrote: >>>> George Herold wrote: >>>>> On Thursday, January 28, 2021 at 8:42:08 AM UTC-5, Phil Hobbs wrote: >>>>>> Rick C wrote: >>>>>>> Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuration there was no gain other than the op amp which has a 1 MHz gain-BW product.. >>>>>>> >>>>>>> So in the frequency range above 100 kHz say, I would expect the control loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.. >>>>>>> >>>>>>> The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended? >>>>>>> >>>>>> Use a BJT, or two in series. My go-to is a single stage, two- or >>>>>> three-pole cap multiplier (two or three RC sections in the base), one in >>>>>> the collector (might as well use that V_BE drop for something useful) >>>>>> and one at the output. You can get sub-nanovolt noise densities that way. >>>>> >>>>> 'one in the collector', scratch scratch, scribble... >>>>> Where does the collector RC go? anywhere I put it looks to increase to resistance >>>>> (power supply source resistance) of the cap multiplier. >>>> You've got a whole V_BE to play with in the collector circuit before you >>>> run into any trouble, so you pick the resistor to drop maybe 0.4V at max >>>> current, and size the cap appropriately. You can also use an LC. >>> Sorry to be so dense, but you're running the R from collector to >>> emitter,(?) with an emitter cap to ground? >>> >>> I must say that a resistor across the transistor seems like the wrong >>> thing to do... >> No, the resistor is in series with the collector, and the capacitor goes >> from there to ground. At very high isolation, junk gets in via >> capacitance and the Early effect otherwise. (BJTs are good that way, >> but not 150 dB worth of good.) > OK so this is after the node that feeds the base RC, > and the Vbe drop of which you spoke is because I can run the collector > a little closer to the emitter than the base is ? (Vce > I wonder if I design cap mults wrong? > 1.) I want the Vin -> base resistance to be as big as possible. > (I'm now wondering about this. the bad thing about big R_base > is it gives the low noise supply a larger source resistance.) > Big R_base gives me a long time constant for a given capacitance > 2.) I then take the max current, (let's say 100mA, cause that is one I did.) > 3.) and a conservative guess at current gain, say 100 for the 2n4401 > 4.) and at max current I want less than/about a volt of drop across R_base > So for this example that's 1V/1mA = 1k ohm. > 5.) I wanted it to have a LF time constant of ~100ms so C_base = 100uF. > Now that I'm almost done, I think it was the 100ms TC that drove the desire > for large R. Two RC stages of 100ms does a nice job of knocking down the > 60 Hz. crud. > 6.) you build the thing, see how it works, tweak if needed. > >> >> It's sometimes useful to put a largish resistor from base to emitter to >> make sure there's enough CB bias for good performance--since it's got a >> BE drop across it, it's a reasonably-constant current source. That's >> needed especially when using a 2-stage cap multiplier, because without >> it the V_BE of the first stage puts the second stage into saturation. >> (Assuming that you use a single RC ladder for both bases, which you should.) > Huh.. do you get phase shift issues inside a two stage thing? > The last thing you want is to make anything close to an oscillator. The two are simply in cascade. There's no feedback to speak of. For a two-stage cap multiplier, you just go Q1 Q2 0-*-R1R1---*----* *--------* *----*--0 | | \ A \ A | | giant CCC ------ ------ | | alpo CCC | | | | | | | | | GND | | bias | | | | | *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-* | | | | | CCC CCC CCC CCC CCC giant CCC CCC CCC CCC CCC alpo | | | | | GND GND GND GND GND (Extra points for using quad pack resistors intelligently.) You pick the bias resistor R6 such that R4+R5 drop enough to keep Q2 from saturating. Good transistors include the 2SD2704K for currents below about 20 mA, and its big, low voltage brother 2SD2114 up to 500 mA or so. They're both low-sat superbeta devices, although slow as molasses, which puts more of a demand on the alpos' high frequency behaviour. You also need some input protection, because folks will inevitably short the input to ground or attach a car battery to it. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com